Carbon Nanotube and Graphene Nanoribbon Interconnects
Azad Naeemi
Georgia Institute of Technology, Atlanta, GA
Email: azad@ece.gatech.edu, Phone: 404-894-4829, Fax: 404-894-5028
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Course Description (2 hrs): Interconnects have long been considered a major limitation for integrated circuits because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. These problems are all exacerbated as interconnect dimensions scale to the dimensions comparable or even smaller than the mean free path of electrons in bulk copper. Carbon nanotubes and graphene nanoribbons are being investigated as potential solutions to the challenges facing nanoscale interconnects because of their extremely large capacity for electrical and thermal conduction. Most of the fascinating properties of carbon nanomaterials can be attributed to their one dimensional nature, the exceptionally strong carbon bonds, and the peculiar bandstructure of graphene.
In this tutorial, compact physical models will be presented for the electronic properties of carbon nanotubes and graphene nanoribbons as functions of their geometry and operating temperature. It will be shown that the temperature coefficient of resistance of carbon nanotubes may vary from negative to positive values depending on their diameters and lengths. The models are used to calculate conductivity of carbon-based nanomaterials and benchmark them against copper wires. The prospect of electronic circuits including both transistors and interconnects on a continuous sheet of graphene will also be discussed.
Bio:
Azad Naeemi received the B.S. Degree in electrical engineering from Sharif University, Tehran, Iran in 1994, and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, Georgia in 2001 and 2003, respectively.
He is currently a Research Engineer at the Microelectronics Research Center at the Georgia Institute of Technology. His primary area of interest is exploring nanotechnology solutions to the challenges facing giga- and terascale systems. He is a member of the International Technology Roadmap for Semiconductors (ITRS) team on Interconnects beyond Cu-Low k.EHe has coauthored two book chapters and more than 50 papers in refereed journals and international conferences. He is a senior member of the IEEE. In 2000, he received the Outstanding Graduate Student Award in the school of Electrical and Computer Engineering at Georgia Tech.
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